NXP Semiconductors /LPC800 /SYSCON /IOCONCLKDIV0

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as IOCONCLKDIV0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DIV0RESERVED

Description

Peripheral clock 0 to the IOCON block for programmable glitch filter

Fields

DIV

IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255.

RESERVED

Reserved

Links

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